Transistors, such as field effect transistors (FETs), may be used on the periphery of a memory device. Some of these transistors might be configured to selectively couple access lines (e.g., word lines) to voltage sources, such as high-voltage sources, for supplying voltages to the access-lines. For example, these transistors might be between the voltage sources and respective access lines. Such transistors might be called string drivers, such as access-line (e.g., word-line) drivers, for example. Some such transistors, for example, might have a relatively high source-drain breakdown voltage Bvdss (e.g., above about 15 volts to about 80 volts or greater).
Some memory devices might include stacked memory arrays, e.g., often referred to as three-dimensional memory arrays. For example, a stacked memory array might include a plurality of vertical strings (e.g., NAND strings) of memory cells, e.g., coupled in series, between a source and a data line, such as a bit line. For example, the memory cells at a common location (e.g., at a common vertical level) might be commonly coupled to an access line (e.g., a local word line), that might, in turn, be selectively coupled to a voltage source by a transistor. A conductive line (e.g., that might be called a runner) might couple an access line to a source/drain of a respective transistor, while another source/drain of the respective transistor might be coupled to a respective voltage source by another conductive line (e.g., runner).
The term vertical may be defined, for example, as a direction that is perpendicular to a base structure, such as a surface of an integrated circuit die. It should be recognized the term vertical takes into account variations from “exactly” vertical due to routine manufacturing and/or assembly variations and that one of ordinary skill in the art would know what is meant by the term vertical.
For some stacked memory arrays, the transistors might be located under (e.g., at a vertical level under) the memory array. However, electric fields that might be produced during fabrication processes in the memory array above the transistors, for example, might have negative effects on various characteristics of the transistors, such as causing changes in the source-drain breakdown voltage Bvdss of the transistors, in the drain-to-source current when the transistor is on, in the drain-to-source saturation current Idss for a saturated condition, e.g., when the control gate of the transistor and the drain of the transistor are at the same voltage, e.g., that is greater than zero volts, etc.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing transistor configurations for use in memory devices with stacked memory arrays and other applications.